Class schedule | HW assignments (Including preparation and review of the class.) | Amount of Time Required | |
---|---|---|---|
1. | Introduction of digital electronic circuits Analog electronic circuits and digital electronic circuits Logic circuits and digital electronic circuits |
P1, P10-12 in the textbook | 120minutes |
2. | Switching characteristics of diode elements and bipolar junction transistors Calculation on circuit parameters of a diode for a switching operation Calculation on circuit parameters of a bipolar transistor for a switching operation |
P51-62 in the textbook | 120minutes |
3. | Pulse operation circuit Pulse operation circuit using a diode Clipping circuit Limiter circuit |
Print material distributed at Share Folder. | 120minutes |
4. | Exercise 1st Switching characteristics of a diode and a bipolar junction transistor |
P1,P10-12, P51-62 in the textbook Print material distributed at Share Folder |
210minutes |
5. | Switching characteristics of a MOS-FET and a CMOS (1) Static characteristics of MOS-FET |
P61-67 in the textbook Print material distributed at Share Folder |
120minutes |
6. | Switching characteristics of a MOS-FET and a CMOS (2) Principle of voltage transfer characteristics of CMOS |
Printing matter | 210minutes |
7. | Mid-term exam and commentary on examination | Reviewing class of 6th and 7th | 400minutes |
8. | Boolean algebra Fundamental theory of the boolean algebra Calculation of the boolean algebra |
P14 -P21 in the textbook | 120minutes |
9. | Fundamental gate circuits and logic functions Fundamental gate circuits for logic circuit A minimum term expression and a max term expression |
P21-25 in the textbook | 120minutes |
10. | Exercise 3rd Fundamental principles and calculations of the Boolean algebra Configuration of fundamental gate circuits using CMOS |
P14-21 in the textbook Print material distributed at Share Folder |
210minutes |
11. | Exercise 4th Configuration of fundamental gate circuits using CMOS |
P14-25 in the textbook Print material distributed at Share Folder |
210minutes |
12. | Design of logic functions using the Karnaugh map Simplified procedure of a digital circuit using the Karnaugh map Simplified procedure in the consideration of the forbidden combination |
P22-31 in the textbook | 120minutes |
13. | Exercise 5th Design of logic functions using the Karnaugh map |
P22-31 in the textbook Print material distributed at Share Folder |
210minutes |
14. | Exercise 5th Design of logic functions using the Karnaugh map |
Reviewing the class of 12th | 400minutes |
Total. | - | - | 2690minutes |
D | Total. | |
---|---|---|
1. | 20% | 20% |
2. | 20% | 20% |
3. | 20% | 20% |
4. | 20% | 20% |
5. | 20% | 20% |
Total. | 100% | - |