|Class schedule||HW assignments (Including preparation and review of the class.)||Amount of Time Required|
|1.||Sugimoto: Design and implementation of a natural language dialogue system
1) Implement a morphological analyzer program
|Complete a morphological analyzer program.||60minutes|
|2.||2) Implement a simple natural language dialogue system||Review a simple natural language dialogue system.||100minutes|
|3.||3) Design and implement a natural language dialogue system||Continue to implement a natural language dialogue system.||100minutes|
|4.||4) Oral presentation and demonstration||Prepare presentation slides and demonstration.||100minutes|
|5.||Igarashi: Approximate solution of combinatorial optimization problems
1) As an example, take up a problem to find an optimal visiting order when a vechile delivers loads to stores. At first, calculate and make a table of the shortest routes between any two stores distributed on a road-map graph.
|Review the Dijkstra algorithm.||90minutes|
|6.||2) Propose an search algorithm for an optimal order of delivering.
Make a presentation of your idea and discuss it with other students.
|Design your algorithm for the optimal problem given in the last class.||90minutes|
|7.||3) Put your algorithm to the test adjusting parameters and analize the results.
Modify your programs if necessary.
|Modify and debug your porgram.||90minutes|
|8.||4) Make a paper on the assignment, your algorithm, discussion and conlusion.||Make a paper and polish it.||90minutes|
|9.||Usami: Design exercise of an LSI chip using FPGA
1) Students learn: a) Design methodology of LSIs; b) What is an FPGA? c) A design method of FPGA with CAD tools.
2) Students design combinational circuits using a design description language "Verilog". In particular, they design an ALU with various functions and verify its operations using a simulator.
|10.||3) Students design sequential circuits using Verilog. In particular, they design a binary counter, implement it in FPGA chip and make it operate.||90minutes|
|11.||4) Students design a one-hot counter using Verilog, implement it in FPGA and make it operate.||90minutes|
|12.||5) Final exercise: Students design a stopwatch circuit, implement it in FPGA and make it operate.||90minutes|
|13.||Sasano: Design and implementation of screen saver description languages
1) A simple language for a simple screen saver
|Review the gcc command and the C language||90minutes|
|14.||2) Design and implementation of screen saver description languages||Study OpenGL and multi-thread programming||90minutes|
|15.||3) Preparation for presenting a screen saver description language and demonstrating an example||Complete writing programs when programming has not finished in the class.||90minutes|
|16.||4) Oral presentation of a screen saver description language and demonstrating an example||Prepare for slides and oral presentation.||90minutes|