Class schedule | HW assignments (Including preparation and review of the class.) | Amount of Time Required | |
---|---|---|---|
1. | Introduction of digital electronic circuit 2 and review of digital electronic circuits 1 Basic gate element Design of a logic function using Karnaugh map |
Reviewing the contents of digital electronic circuits 1. P1-67 in the textbook |
90minutes |
2. | Typical combination circuits Multiplexer, Comparator, Adder |
P68-98 in the textbook | 120minutes |
3. | Exercise (1st) Typical combination circuits |
Reviewing the 1st and 2nd classes. | 180minutes |
4. | Sequential circuits Introduction of sequential circuits Description of the sequential circuit behavior Design of the sequential circuit using delay elements |
P68 in the textbook Print material distributed at Share Folder |
120minutes |
5. | Exercise 2nd Design of the sequential circuit using delay elements |
Reviewing the 4th class | 180minutes |
6. | Filp-Flop(FF) Configuration and behavior of RS-FF Operation of positive edge trigger and of negative edge trigger Synchronous sequential circuit and asynchronous one Behavior of JK-FF and D-FF |
P99-118 in the textbook | 120minutes |
7. | Exercise 3rd Basic configuration and behavior of RS-FF Description of the sequential circuit behavior using timing chart |
Reviewing the 6th class | 240minutes |
8. | A sequential circuit using FF and typical sequential circuits(1) Asynchronous counter and synchronous one Design of count using JK-FF Delay time of FF |
P119 -128 in the textbook | 120minutes |
9. | A sequential circuit using FF and typical sequential circuits(2) Shift register Design of counter Ring counter, Jonson counter and grey code counter |
P128-140 in the textbook | 120minutes |
10. | Exercise 4th Ring counter, Jonson counter and grey code counter Design of count using JK-FF Creation of timing chart for a sequential circuit |
Reviewing the 8th and 9th classes | 240minutes |
11. | Final examination Practice of designing digital circuits using HDL(1) (Lecture and practice in PC room) Programming syntax of verilog HDL Structural description |
Reviewing the class from 1th to 10th p.1-83 in the textbook 2 |
400minutes |
12. | Practice of designing digital circuits using HDL(2) (Lecture and practice in PC room) Behavior description No-blocking sentence and blocking one Control structure sentence |
P83-99 of the textbook 2 | 120minutes |
13. | Practice of designing digital circuits using HDL(3) (Lecture and practice in PC room) hierarchical design Description of testbench for verification of the circuit |
P137-177 of the textbook 2 | 120minutes |
14. | Practice of designing digital circuits using HDL(4) (Lecture and practice in PC room) Programming and simulation on a simple sequential circuit |
P101-135 of the textbook 2 | 420minutes |
Total. | - | - | 2590minutes |
D | Total. | |
---|---|---|
1. | 25% | 25% |
2. | 25% | 25% |
3. | 25% | 25% |
4. | 25% | 25% |
Total. | 100% | - |