CPU chips are the most important components in computer systems and their performance has been continuing to grow. In this
lecture, we study representative computer architectures that are actually used in high performance processor chips. Furthermore,
through designing hardware components (i.e. function units) and simulations, we analyze and discuss how the hardware structure
influences the performance.
The material to read is provided in pdf at Scomb and Reading Assignments are directed in advance. To help understanding in reading, several basic questions are also provided about the contents of the pre-directed reading material. At every class, students are divided into groups and discuss what he/she understood through the reading material and his/her answer to the questions. Discussion is made in each breakout room of Zoom. Then, students give presentations in group order. The instructor checks the presentations and gives lecture/comments to make up for missing content in their presentation.
The material to read is provided in pdf at Scomb and Reading Assignments are directed in advance. To help understanding in reading, several basic questions are also provided about the contents of the pre-directed reading material. At every class, students are divided into groups and discuss what he/she understood through the reading material and his/her answer to the questions. Discussion is made in each breakout room of Zoom. Then, students give presentations in group order. The instructor checks the presentations and gives lecture/comments to make up for missing content in their presentation.
To understand technologies in computer architecture to achieve high performance through case studies of real processor chips
- To understand representative computer architectures that are actually used in high performance CPU chips
- To understand how the hardware structure influences the performance through a design project of hardware components
- To be able to actually design a hardware component used in a CPU and evaluate its performance
| Class schedule | HW assignments (Including preparation and review of the class.) | Amount of Time Required | |
|---|---|---|---|
| 1． | Guidance and overview of high-performance architecture | Fundamentals of computer architecture | 80minutes |
| 2． | Technology/power trends and changes in computer architecture | Review of changes in computer architecture, Instruction-level parallelism, Data-level parallelism and Domain-Specific architecture | 200minutes |
| 3． | Instruction-level parallelism, Pipelining and Dynamic scheduling techniques | Review of pipelining, hazard and concept of dynamic scheduling | 200minutes |
| 4． | Dynamic scheduling and issues | Review of techniques and issues in dynamic scheduling | 200minutes |
| 5． | Superscalar technology (1) | Review of concept of superscalar | 200minutes |
| 6． | Superscalar technology (2) | Review of basic components in superscalar architecture | 200minutes |
| 7． | Case studies of superscalar processors (1) | Review of superscalar in Intel Pentium processor | 200minutes |
| 8． | Case studies of superscalar processors (2) | Review of superscalar in Intel Pentium2 and Pentium4 processors | 200minutes |
| 9． | Design project on CPU datapath components (1) | Review of structure of an adder; Designing a ripple-carry adder circuit in Verilog HDL and conducting logic simulation | 200minutes |
| 10． | Design project on CPU datapath components (2) | Review of a carry-lookahead adder (CLA) and carry-select adder; Designing a CLA circuit in Verilog HDL and conducting logic simulation | 200minutes |
| 11． | Design project on CPU datapath components (3) | Review of parallel prefix adders | 200minutes |
| 12． | Data-level parallelism, Vector and SIMD architectures | Review of data-level parallelism in Vector architecture; SIMD architecture for multi-media processing | 200minutes |
| 13． | Domain-Specific architecture | Review of Domain-Specific architecture for Deep Neural Networks and Google's Tensor Processing Unit | 200minutes |
| 14． | Presentation of the design and analysis results | Design of high-speed adder and evaluation from performance and area | 200minutes |
| Total. | - | - | 2680minutes |
| Class participation and Submitted reports | Presentation on the design project | Total. | |
|---|---|---|---|
| 1. | 20% | 80% | 100% |
| 2. | 0% | ||
| Total. | 20% | 80% | - |
If the student submits the design competition assignment and the adder which he/she designed based on the method introduced
in the class works correctly and makes the presentation on it, the score 60% is given. Upper score than 60% is given depending
on the achieved circuit speed and the area of his/her adder.
J. Hennessey and D. Patterson, “Computer Architecture, Sixth Edition: A Quantitative Approach”, Morgan Kaufmann Publishers,
2017.
J. Shen, M. Lipasti, “Modern Processor Design: Fundamentals of Superscalar Processors”, McGraw-Hill, 2005.
D. Patterson and J. Hennessey, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann Publishers, 2017.
J. Shen, M. Lipasti, “Modern Processor Design: Fundamentals of Superscalar Processors”, McGraw-Hill, 2005.
D. Patterson and J. Hennessey, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann Publishers, 2017.
- Course that cultivates an ability for utilizing knowledge
- Course that cultivates a basic problem-solving skills
| Work experience | Work experience and relevance to the course content if applicatable |
|---|---|
| Applicatable | About 20 years of working experience at Toshiba, where he was actually involved in the design of CPU chips |
- 4.QUALITY EDUCATION
- 7.AFFORDABLE AND CLEAN ENERGY
Last modified : Sat Aug 29 04:09:37 JST 2020