Course title
E02906002
Digital Circuit

andou yoshinobu Click to show questionnaire result at 2019
Course description
Digital circuits are widely used in computers, network communication equipment.
Digital circuits are supporting today's information systems.
In this class, you can learn about basic technology of digital circuits.
The purpose of this class is that you can design and analyze about digital circuits.
Purpose of class
The purpose of this class is that you can design and analyze about digital circuits.
Goals and objectives
  1. You can explain about basic logic gate.
  2. You can design basic logic circuits.
  3. You can simplify logical circuits.
  4. You can explain about state translation of sequential circuits.
  5. You can design synchronous counter circuits.
Language
Japanese
Class schedule

Class schedule HW assignments (Including preparation and review of the class.) Amount of Time Required
1. Digital information 1
(Digital value and analogue value, N-ary number, numerical notation)
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about difference of digital value and analogue value. 190minutes
2. Digital information 2
(Logic gate IC, Electrical characteristic of TTL and C-MOS).
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about electrical characteristic of TTL and C-MOS. 190minutes
3. Digital information 3
(Binary number and octal number and hexadecimal number, Two's complement, .).
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about binary number and octal number and hexadecimal number. 190minutes
4. Logical operation 1
(Venn diagram, Karnaugh map, Boolean algebra)
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about Boolean algebra. 190minutes
5. Logical operation 2
Disjunctive canonical form and conjunctive normal form.
Truth table and logical equation.
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about disjunctive canonical form and conjunctive normal form. 190minutes
6. Simplifying logical circuit 1.
Simplifying practice of logical circuits by using Karnaugh map.
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about simplifying method of logical circuits by using Karnaugh map. 190minutes
7. Simplifying logical circuit 2.
Simplifying practice of logical circuits by using Quine-McCluskey algorithm.
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about simplifying method of logical circuits by using Quine-McCluskey algorithm. 190minutes
8. Combinational circuit 1(encoder circuit, decoder circuit, comparator circuit and parity check circuit)
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about encoder circuit and decoder circuit. 190minutes
9. Combinational circuit 2
(half adder and full adder)
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about half adder and full adder. 190minutes
10. Sequential circuit 1
(state transition table and state Transition Diagram.).
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about state transition table and state Transition Diagram. 190minutes
11. Sequential circuit 2 (Binary counter).
JK Flip Flop, D Flip Flop, T Flip Flop
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about function and type of flip flop. 190minutes
12. Synchronous counter circuit.
Input equation and output equation of flip flop.
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about input equation and output equation of flip flop. 190minutes
13. Design method of synchronous counter circuit.
Short Report (Exercise) and Short Report (Home work)
Pre-reading and reviewing referential books and web sites about design method of synchronous counter circuit. 190minutes
14. Final exam and some explanation about final exam Review about all contents of this class and prepare final exam. 190minutes
Total. - - 2660minutes
Relationship between 'Goals and Objectives' and 'Course Outcomes'

Short report (Exercise) Short report (homework) Final exam Total.
1. 4% 2% 14% 20%
2. 4% 2% 14% 20%
3. 4% 2% 14% 20%
4. 4% 2% 14% 20%
5. 4% 2% 14% 20%
Total. 20% 10% 70% -
Evaluation method and criteria
All goals and objectives are evaluated at the total point of the short reports (exercise) and short report (home work) and final exam. The score of this class is calculated from total score of Short report (exercise)(20%) and Short report (home work)(10%) and final exam(70%). If you take 60% or more than 60% of total scores, you can pass this class.
Textbooks and reference materials
Please read the textbooks and reference materials.
"Class Note of Digital circuit for understanding basic theory" Author: Ando, Iguchi, Tatsuta, Hiraguri, Supervisor Eiji Watanabe (Ohmsha)
Prerequisites
You should take “engineering practice” before this class.
Office hours and How to contact professors for questions
  • While the class and after class, you can ask your question. Every time you can send me Email about question.
  • Email: yando@sic.shibaura-it.ac.jp
  • Office hour (Ando): Tuesday lunchtime (Please be sure to make an appointment with me in advance.)
Regionally-oriented
Non-regionally-oriented course
Development of social and professional independence
  • Course that cultivates an ability for utilizing knowledge
Active-learning course
More than one class is interactive
Course by professor with work experience
Work experience Work experience and relevance to the course content if applicatable
N/A N/A
Education related SDGs:the Sustainable Development Goals
  • 4.QUALITY EDUCATION
  • 9.INDUSTRY, INNOVATION AND INFRASTRUCTURE
Last modified : Sat Mar 21 12:16:16 JST 2020