Report | Total. | |
---|---|---|
1. | 25% | 25% |
2. | 25% | 25% |
3. | 25% | 25% |
4. | 25% | 25% |
Total. | 100% | - |
Class schedule | HW assignments (Including preparation and review of the class.) | Amount of Time Required | |
---|---|---|---|
1. | Sugimoto: Design and implementation of a natural language dialogue system 1) Implement a morphological analyzer program |
Complete a morphological analyzer program. | 60minutes |
2. | 2) Implement a simple natural language dialogue system | Review a simple natural language dialogue system. | 100minutes |
3. | 3) Design and implement a natural language dialogue system | Continue to implement a natural language dialogue system. | 100minutes |
4. | 4) Oral presentation and demonstration | Prepare presentation slides and demonstration. | 100minutes |
5. | Watabe: Exercise on algorithm for quantum computer 1) Develop the environment for Jupyter notebook and Qiskit. 2) Understand the principle of quantum mechanics and properties of single qubit. |
Review the principle of quantum mechanics and properties of quantum bits. | 90minutes |
6. | 3) Understand gate operations for single qubit and run the Qiskit. In particular, understand properties of the X, Y, Z, H gates. | Review gate operations for the single qubit. | 90minutes |
7. | 4) Understand gate operations for multi qubits and run the Qiskit. In particular, understand properties of CNOT gate. | Review gate operations for multi-qubits. | 90minutes |
8. | 4) By combininng gate operations for the single qubit and the multi-qubits, make a quantum cirquit on the Qiskit for the quantum algorithm such as the quantum teleportation. | Review gate operations for single qubit and multi-qubits. | 90minutes |
9. | Usami: Design exercise of an LSI chip using FPGA 1) Students learn: a) Design methodology of LSIs; b) What is an FPGA? c) A design method of FPGA with CAD tools. 2) Students design combinational circuits using a design description language "Verilog". In particular, they design an ALU with various functions and verify its operations using a simulator. |
Design an ALU with various functions. | 90minutes |
10. | 3) Students design sequential circuits using Verilog. In particular, they design a binary counter, implement it in FPGA chip and make it operate. | Design a binary counter. | 90minutes |
11. | 4) Students design a one-hot counter using Verilog, implement it in FPGA and make it operate. | Design a one-hot counter. | 90minutes |
12. | 5) Final exercise: Students design a stopwatch circuit, implement it in FPGA and make it operate. | Design a stopwatch circuit. | 90minutes |
13. | Sasano: Design and implementation of screen saver description languages 1) A simple language for a simple screen saver |
Review the gcc command and the C language | 90minutes |
14. | 2) Design and implementation of screen saver description languages | Study OpenGL and multi-thread programming | 90minutes |
15. | 3) Preparation for presenting a screen saver description language and demonstrating an example | Complete writing programs when programming has not finished in the class. Prepare for slides and oral presentation. | 90minutes |
16. | 4) Oral presentation of a screen saver description language and demonstrating an example | Oral presentation | 90minutes |
Total. | - | - | 1440minutes |
ways of feedback | specific contents about "Other" |
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Feedback in the class |
Work experience | Work experience and relevance to the course content if applicable |
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N/A | N/A |