Integrated Circuits

Course title

G0032000

Integrated Circuits

Middle-level Diploma Policy (mDP)

Program / Major	mDP	Goals	Courses
Fundamental Mechanical Engineering	F	産業界や社会の要請を把握して解決するべき課題を設定し、さまざまな工学分野の知識を関連付けながら設計生産技術を活用することで、立案した構想に従って研究を進め課題を解決することができる。	Sub
Advanced Mechanical Engineering	F	産業界や社会の要請を把握して解決するべき課題を設定し、機械工学の学理を応用して異分野を含む融合分野で革新的な機能を創成することができる。	Sub
Environment and Materials Engineering	B	地球環境や地域社会との調和を見据えて、さまざまな工学分野に関わる問題を解決することができる。	Sub
Chemistry and Biotechnology	B	地球環境や地域社会との調和を見据えて、さまざまな工学分野に関わる問題を解決することができる。	Sub
Electrical Engineering and Robotics	D	電気工学や関連する工学の技術分野を課題に適用し、社会の要求を解決するために応用することができる。	Sub
Advanced Electronic Engineering	D	電子工学に関する基礎知識と、応用する能力を身に付けることができる。	Main
Information and Communications Engineering	F	社会のニーズに対して技術課題を主体的に発見し、工学分野における分野横断的な知識も活用しつつ、計画的・継続的に取り組んで課題を達成することができる。	Sub
Urban Infrastructure and Environment	G	⼟⽊⼯学における現実の問題について、⼯学・専⾨基礎知識を⽤いて理解・解決することができる。	Sub

Purpose of class

This course aims to help students understand the main components of integrated circuits, understand the overall LSI (Large-Scale Integration) design flow including system-on-chip (SoC), and acquire the foundational knowledge required to use LSI design tools. Students will also develop practical skills by handling small design examples with CAD tools.

Course description

Integrated circuits are used in a wide range of systems, and their use in IoT (Internet of Things) is expanding through LSIs such as system-on-chip (SoC). To design integrated circuits, students need to understand not only circuit technologies (e.g., analog and digital circuits) but also physical design, RTL-based design, high-level synthesis, design verification, and test technologies.

Goals and objectives

Understand the basic elements that make up CMOS integrated circuits, what a system LSI is, and the LSI design flow.
Understand layout design methods for LSIs.
Understand behavior‑level (RTL) design methods for LSIs using a hardware description language (e.g., Verilog HDL).
Understand timing design requirements and specifications based on the concept of synchronous circuits (e.g., clocking, setup/hold constraints).
Understand low-power design techniques for LSIs.

Relationship between 'Goals and Objectives' and 'Course Outcomes'

	Short Test	Report	Final Exam	Total.
1.	6%		8%	14%
2.	6%	10%	8%	24%
3.	6%	12%	5%	23%
4.	4%	15%	10%	29%
5.	4%		6%	10%
Total.	26%	37%	37%	-

Evaluation method and criteria

Short tests: 26%, Report assignments: 37%, Final exam: 37% (total 100 points). A total score of 60 points or higher is required to pass.

Short tests: Students who are able to solve the comprehension checks based on the handouts will receive 60%.
Report assignments: Submitting all required items will be evaluated at 60%.
Final exam: Students who are able to reliably solve the exercises in the handouts will receive 60%.

Language

Japanese

Class schedule

	Class schedule	HW assignments (Including preparation and review of the class.)	Amount of Time Required
1.	Guidance What is an Integrated Circuit? What is a System LSI (1) Topics ･Evolution toward system LSIs ･Roles of system LSIs	Read Chapter 1 “What is a System LSI?”	70minutes
1.		Review the lecture content and complete the comprehension check	120minutes
2.	What is a System LSI (2) Topics ･LSI structure and design items ･Types of system LSI implementations ･High integration ･Miniaturization and related issues	Read Chapter 1 “What is a System LSI?”	70minutes
2.		Review the lecture content and complete the comprehension check	120minutes
3.	System LSI Design Flow Topics ･Design procedures for system LSIs ･Trends in design technologies	Read Chapter 2 “System LSI Design Flow”	30minutes
		Review the lecture content and complete the comprehension check	30minutes
		A short test covering Lectures 1–3 will be administered; review thoroughly	130minutes
4.	Short Test on System LSI and System LSI Design Flow Layout Design (1) Topics ･What is layout design? ･Layout methodologies	Read Chapter 6 “Layout Design (1)”	70minutes
4.		Review the lecture content and complete the comprehension check	120minutes
5.	Layout Design (1) Topics ･Layout of modules (cells) ･Library development of modules (cells) Layout Design (2) Topics ･Chip‑level layout design	Read Chapter 6 “Layout Design (2)”	70minutes
5.		Review the lecture content and complete the comprehension check	120minutes
6.	Layout Design (2) Topics ･Physical design verification ･DFM (Design for Manufacturability) technologies ･Summary and future issues	Read Chapter 6 “Layout Design (2)”	30minutes
		Review the lecture content and complete the comprehension check	30minutes
		A short test covering Lectures 4–6 will be administered; review thoroughly	130minutes
7.	Short Test on Layout Design Behavior‑Level IC Design Using an HDL (1) Topics ･What is Verilog HDL? ･Logic values and constant formats in Verilog HDL ･Describing adders using the addition operator ･Describing adders using a full‑adder	Read the corresponding parts of the handouts	70minutes
7.		Review the lecture content and install a Verilog simulator	120minutes
8.	Behavior‑Level IC Design Using an HDL (2) Topics ･Describing D flip‑flops ･Describing D latches ･Two assignment methods to registers ･Asynchronous vs. synchronous reset ･Structure and operation of FPGAs	Read the corresponding parts of the handouts	70minutes
8.		Review the lecture content and confirm the Verilog simulator is working	120minutes
9.	Behavior‑Level IC Design Using an HDL (3) Topics ･Testbenches used with a Verilog simulator ･Design exercise: adder using a Verilog simulator ･Design exercise: D flip‑flop using a Verilog simulator Report Assignment 1	Read the corresponding parts of the handouts; Report Assignment 1 will be announced after the lecture	30minutes
		Review the lecture content	30minutes
		Creating a report	130minutes
10.	Behavior‑Level IC Design Using an HDL (4) Topics ･Designing a simple calculator in hardware Timing Verification Topics ･Methods for calculating delays in LSIs ･Synchronous design and timing issues ･Timing verification methods ･Layout design and timing optimization methods ･Timing verification in deep‑submicron Report Assignment 2	Read Chapter 7 “Timing Verification”; Report Assignment 2 will be announced after the lecture	30minutes
		Review the lecture content and complete the comprehension check	30minutes
		Creating a report	130minutes
11.	Low‑Power Design (1) Topics ･Why low‑power design is necessary ･Internal structure of SoCs - where power is consumed ･Fundamentals of power consumption in CMOS ･Power analysis techniques ･Design flow and key points for power reduction	Read Chapter 8 “Low‑Power Design (1)”	70minutes
		Review the lecture content and complete the comprehension check	120minutes
		Creating a report	130minutes
12.	Low‑Power Design (2) Topics ･Low‑power techniques in logic synthesis ･Low‑power techniques in RTL design ･Low‑power design at the architecture level ･Cross‑stage power‑reduction techniques across the design flow ･Directions and challenges in low‑power technologies	Read Chapter 8 “Low‑Power Design (2)”	70minutes
		Review the lecture content and complete the comprehension check	120minutes
		Creating a report	130minutes
13.	Design for Testability (DFT) Topics ･Necessity of design for testability ･Methods for design for testability ･Test strategies for SoCs ･Future issues Advanced Physical Design Topics ･Variation issues in LSIs ･SSTA (Statistical Static Timing Analysis) and physical design ･Parameter extraction ･Issues associated with signal‑speed improvement	Read Chapter 9 “Design for Testability” and Chapter 10 “Advanced Physical Design”	70minutes
		Review the lecture content and complete the comprehension check	120minutes
		Creating a report	130minutes
14.	Summary of LSI Design and Future Issues Topics ･Review and confirmation of the course content Final Exam	Final Exam covers Lectures 1–13, review thoroughly. Detailed instructions will be given at the end of Lecture 13. Study for the final exam	160minutes
		Review the lecture content and complete the comprehension check	120minutes
		Creating a report	130minutes
Total.	-	-	3270minutes

Feedback on exams, assignments, etc.

ways of feedback	specific contents about "Other"
Feedback in the class

Textbooks and reference materials

Materials based on ”System LSI Design: LSI Design” published by Semiconductor Technology Academic Research Center (STARC) will be distributed during the lecture.
Using Verilog HDL is planned, so the reference book is useful. For example, Kobayashi, hdLab: “CQ Endeavor Verilog HDL”, CQ Publishing
For the operation of MOS transistors, Hara, et al.: ”Theory of operation of MOS transistors”, Kindai kagaku sha Co., Ltd., 1980
Regarding CMOS circuits, Hara, et al .: ”Basics of MOS Integrated Circuits”, Kindai kagaku sha Co., Ltd., 1992

Prerequisites

It is desirable to take courses such as electric circuits 1-3, analog electronic circuits 1 and 2, digital electronic circuits, and semiconductor engineering. In addition, it is desirable to be able to operate the computer (create a simple program, compile and execute).

Office hours and How to contact professors for questions

Questions and consultations will be accepted at the classroom from 12:30 to 12:40 immediately after the lecture.
If you would like to have a consultation on the Zoom, please contact me by e-mail in advance and I will respond from 15:20 to 15:40 after the lecture.

Regionally-oriented

Non-regionally-oriented course

Development of social and professional independence

Course that cultivates an ability for utilizing knowledge
Course that cultivates a basic problem-solving skills

Active-learning course

More than one class is interactive

Course by professor with work experience

Work experience	Work experience and relevance to the course content if applicable
Applicable	Based on the work experience, which is Integrated and electronic circuit development at an automotive company, design methods of the recent integrated and electronic circuit are taught.

Education related SDGs:the Sustainable Development Goals

9.INDUSTRY, INNOVATION AND INFRASTRUCTURE

Last modified : Sat Mar 14 13:51:58 JST 2026